INSPIRE : A general purpose network simulator generating system for massively parallel processors

نویسندگان

  • Taisuke Boku
  • Tomoki Harada
  • Takeshi Sone
  • Hiroshi Nakamura
  • Kisaburo Nakazawa
چکیده

In this paper, we describe a general purpose network simulator generation system INSPIRE (Interconnection Network Simulator with Programmable Interaction and Routing for performance Evaluation), for massively parallel processing systems. In this system, a user describes various characteristics of the target network, for instance, network resources, network topology, and routing algorithm, in a dedicated language called NDL (Network Description Language). A user also can describe the behavior of PU's (Processing Units) in C language with procedural manner to simulate not only simple message transfer patterns but also actual application. The network speci cation le in NDL is translated into a C language source le, then combined with PU behavior description le and the kernel object code for INSPIRE to create a dedicated network simulator. It is executed automatically and it helps reducing a large man-power for writing simulators for various kinds of network and PU behavior. A simulator created by INSPIRE simulates the behavior of all PU's, message sent/received by PU's, and message transfer and con ict on the network. Finally, various statistics on message passing and PU behavior are shown as the simulation result. We have implemented INSPIRE on UNIX workstations, and con rmed that the execution speed of generated simulator is enough high compared with dedicated simulators. We also con rmed that NDL is powerful enough to describe various kinds of direct and indirect network topologies.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Real Time Dynamic Simulation of Power System Using Multiple Microcomputers

Recent developments in the design and manufacture of microcomputers together with improved simulation techniques make it possible to achieve the speed and accuracy required for the dynamic simulation of power systems in real time. This paper presents some experimental results and outlines new ideas on hardware architecture, mathematical algorithms and software development for this purpose. The ...

متن کامل

GPGPU-Accelerated Instruction Accurate and Fast Simulation of Thousand-core Platforms

Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, performance (and power) evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation...

متن کامل

A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA

The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA (Cellular Automata) model. In differentiation to the CA model the neighbors are not fixed and local, they are variable and global. The GCA model is applicable to a wide range of parallel algorithms. In this paper a...

متن کامل

Practical Simulation of Large-Scale Parallel Programs and Its Performance Analysis of the NAS Parallel Benchmarks

A simulation technique for very large-scale data parallel programs is proposed. In our simulation method, a data parallel program is divided into computation and communication sections. When the control ow of the parallel program does not depend on the contents of network messages, the computation time on each processor is calculated independently. An instrumentation tool called EXCIT is used t...

متن کامل

A latency simulator for many-core systems

In this paper we present MCoreSim, an open-source simulation framework for massively parallel and many-core computing systems based on OMNeT++. The simulator supports tile-based architectures with distributed memory and meshbased interconnects. Its primary purpose is to allow for investigations on the impact of the heterogeneous in-chip communication latencies, as arising due to the network-on-...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1995